This invention relates generally to testing digital semiconductor devices and pertains particularly to providing limited probes device testing for high pin count digital devices.
To assure high reliability, it is necessary when designing complex digital application specific integrated circuits (ASIC's) to design in testability. Testability is a property of a circuit, board or system that enables non-destructive testing. Custom and complex digital ASIC's often have a very high pin count which requires very high pin count conventional automatic test equipment (ATE) to perform comprehensive testing. However it is very expensive to build and maintain a high pin count ATE machine to support testing of high pin count digital ASIC's.
Design for test (DFT) techniques seek to reduce the complexity of design for test purposes and to keep the cost of test generation within reasonable bounds. The object of DFT is to improve the reliability of hardware.
Scan design is a DFT technique which utilizes a scan storage element, such as a specialized flip-flop or latch, that allows data to be scanned in for control and to be scanned out for observation and can be activated in scan mode for test purposes. The scan storage elements are generally connected in serial fashion to form an internal scan chain.
Boundary scan is a test technique which uses shift registers (scan flip-flops) placed adjacent to each device signal pin and the internal logic. These shift registers can control and observe signal values present at each input and output pin and are connected together in serial fashion to form a Data Register (DR) chain called a boundary scan register (BSR) chain. For general information on the use of boundary scan registers, see for example, "The Test Access Port and Boundary-Scan Architecture", Published by IEEE Computer Society Press; IEEE Std 1149.1-1990, IEEE, Inc. 345 E. 47th St., New York, N.Y. 10017, October 1993; U.S. Pat. No. 5,115,191, issued to T. Yoshimori for "Testing Integrated Circuit Capable of Easily Performing Parametric Test on High Pin Count Semiconductor Device", May 19, 1992; U.S. Pat. No. 5,412,260 issued to C. Tsui for "Multiplexed Control Pins For In-System Programming And Boundary Scan State Machines In A High Density Programmable Logic Device", on May 2, 1995.
Current circuits used for boundary scan test techniques are designed for use when the circuit is connected within a board or system. During testing, the input pins of each integrated circuit within a board being tested are held to appropriate voltage levels.
However, when individual circuits, such as complement metal oxide semiconductor (CMOS) devices, are tested before being attached to a circuit board, for example, when individual circuits are tested during wafer sort, the input pads of the circuits float when not held to appropriate voltage levels either by automatic test equipment or other means. This makes the use of boundary scan techniques impractical for use when testing circuits that are not yet placed in a circuit board.